1. Field of the Invention
The invention relates to a semiconductor memory, particularly to a semiconductor memory having a redundant memory cell array.
2. Description of Related Art
A read/write memory (hereinafter referred as RAM) and a read only memory (hereinafter referred after as ROM) are known as a prior art semiconductor memory. A dynamic random access memory (hereinafter referred after as DRAM) or a static random access memory (hereinafter referred after as SRAM) are known as the RAM An electrically erasable programmable ROM (hereinafter referred after as EEPROM) or a mask ROM or the like are known as the ROM.
In the semiconductor memory set forth hereinbefore, particularly a RAM having a redundant memory cell array is known. The RAM having the redundant memory cell array is, for example, disclosed in the following document.
(1) Japanese Patent Laid-Open Publication No. 2-210686.
As disclosed in this document, a redundant memory cell array is remedy means which is used when faulty memory cells, faulty bit lines, or faulty word lines are present in a normally used memory cell array (hereinafter referred to as normal memory cell array) and the configuration using the same.
That is, when address information for selecting the faulty memory cells, the faulty bit lines or the faulty word lines is specified, the redundant memory cell array or the configuration using the same is selected without selecting the faulty memory cells, the faulty bit lines, or the faulty word lines (these faults are hereinafter referred to as faults). Even if there are faults in the normal memory cell array or the configuration using the same, the provision of the redundant memory cell array and the configuration using the same allows such semiconductor memory to operate in the same manner as the semiconductor memory having no faults.
The aforementioned faults can be found when the write/read test is made on the normal memory cell array. The test is made by writing arbitrary data on memory cells constituting the normal memory cell array and reading written data. It is possible to verify the presence or absence of the faults from the coincidence condition between the write data and read data.
If the test verifies the presence of faults, a redundant memory cell array is used instead of the faulty memory cells, the faulty bit lines or the faulty word lines.
For a write/read test on a redundant memory cell array, if the redundant memory cell is replaced by the faults, such test could be made on a part of the redundant memory cell array which has been replaced by the faults. That is, the read/write test to be made in advance on the redundant memory cell array has been difficult before the replacement thereof. Accordingly, if faults are found in a part of the redundant memory cell array which has been used for the replacement by the faults, such faults are required to be replaced again by another part of the redundant memory cell array.
To prevent the problems set forth hereinbefore, a write/read test is required to be made on the redundant memory cell array before it is replaced by faults like the write/read test to be made on a normal memory cell array.
In addition to satisfying the above requirement, it should be considered that the increase of a circuit configuration for satisfying the requirement is reduced to the utmost, the normal operation (write/read operation on the normal memory cell array) is not influenced, complexity of test operation and test time are reduced to the utmost.
It is a first object of the invention to provide a semiconductor memory capable of making a write/read test on a redundant memory cell array before replacing it by faults like the write/read on the normal memory cell array.
It is another object of the invention to reduce the increase of a circuit configuration to the utmost for achieving the first object.
It is still another object of the invention to provide a semiconductor memory capable of achieving the first object and of not influencing a normal operation.
It is still another object of the invention to provide a semiconductor memory capable of achieving the first object and of reducing complexity of test operation to the utmost.
It is still another object of the invention to provide a semiconductor memory capable of achieving the first object and of reducing test time to the utmost.